Low-Complexity Wallace Multiplier Using Energy-Efficient Full Adder Based On Carbon Nanotube Technology

In high speed applications, multipliers and their associated circuits like accumulators, half adders, and full adders consume a significant portion. Therefore, it is necessary to increase their performance as well as size efficiency. In order to reduce the hardware complexity which ultimately reduces an area and power, energy efficient full adders plays crucial role in Wallace tree multiplier. Reduced Complexity Wallace multiplier (RCWM) will have fewer adders than Standard Wallace multiplier (SWM).The Reduced complexity reduction method greatly reduces the number of half adders with 75-80% reduction in an area of half adders than standard Wallace multipliers. In RCWM and SWM, at the last stage Carry Propagating Adder (CPA) is used. This paper proposes use of high speed, low power full adder based on Carbon Nanotube technology in reduced complexity Wallace Multiplier at the place of Conventional Full adder in order to reduce power, area and improvement in speed. Keywords— Wallace Multiplier, energy efficient CNTfull adders, High speed multiplier, CMOS full adder, Carbon Nanotube Field Effect Transistor, High Speed, Low Power INTRODUCTION In digital electronic world, power consumption and delay improvement are the most important parameters of a circuit. Digital signal processing (DSP) and image processing, multiplier play a crucial role. In image processing fast Fourier transform (FFT) is one of the most important transform often used. In Fast Fourier transform, computational process requires large number of multiplication and addition operation. The execution of these algorithms requires dedicated MAC and Arithmetic and Logic Unit (ALU) architectures. Multipliers and adders are the key element of these arithmetic units [9]as they lie in the critical path. Many researchers have tried to implement increasingly efficient multiplier. They aim at offering low complexity, low power consumption and high speed. One such multiplier is Standard Wallace Multiplier (SWM) [3]. SWM is fully parallel version of the multiplier, the carry save adders (CSA) used in SWM are conventional full adders whose carries are not connected. SWM also uses half adders in reduction phase. Reduced complexity Wallace multiplier (RCWM) [1] reduced number of half adders used in SWM with a slight increase in full adders to reduce the number of gates. Both the multipliers SWM and RCWM have same number of stages and delay is also same. The complementary CMOS and CPL designs are two conventional Adders based on CMOS structure. Based on transmission function and transmission gate, TFA and TGA designs were implemented. The other designs are classified as Hybrid designs. This paper proposes use of high speed, low power full adder based on Carbon Nanotube technology (CNT)[4] in reduced complexity Wallace multiplier at the place of carry propagating adder in order to reduce power, area and improvement in speed. CARBON NANOTUBE FIELD EFFECT TRANSISTORS (CNFETS) Carbon nanotube field effect transistor (CNTFET) uses CNT as their semiconducting channels. A single-wall CNT (SWCNT) consists of one cylinder only, and the simple manufacturing process of this device makes it very promising for alternative to MOSFET. The gate-to-source voltage that generates the same reference current is taken as the threshold voltage for the transistor that has different chirality. CNTFETs provide a unique opportunity to control threshold voltage by changing the diameter of the CNT or the chirality vector. Fig. 1 shows the threshold voltage of both P-CNTFET and N-CNTFET obtained from simulation for various chirality vectors (various n for m = 0) [11].The CNTFETs are particularly attractive due to possibility of near ballistic channel transport, easy application of high–k gate insulator and novel device physics. Although most of the work on CNTFETs has concentrated so far on their d.c. properties, the a.c. properties are technologically most relevant. Theoretically, it is predicted that a short nanotube operating in the ballistic regime, and the quantum capacitance limit should be able to provide gain in the THz range [12]. International Journal of Engineering Research and General Science Volume 3, Issue 2, March-April, 2015 ISSN 2091-273